In this paper, we propose an approach to estimate the Worst Case Response Time (WCRT) of each task in a preemptive multi-tasking single-processor real-time system with an L1 cache. The approach combines inter-task cache eviction analysis and intra-task cache access analysis to estimate the number of cache lines that can possibly be evicted by the preempting task and also be accessed again by the preempted task after preemptions (thus requiring the preempted task to reload the cache line(s)). This cache reload delay caused by preempting tasks is then incorporated into WCRT analysis. Two sets of applications are used to test our approach. Each set of applications contains three tasks. The experimental results show that our approach can ...
Abstract — Schedulability analysis for real-time systems has been the subject of prominent research ...
28th Euromicro Conference on Real-Time Systems (ECRTS 2016). 5 to 8, Jul, 2016. Toulouse, France.Out...
Hard real-time systems are typically composed of multiple tasks, subjected to timing constraints. To...
In this paper, we propose an approach to estimate the Worst Case Response Time (WCRT) of each task i...
Abstract. In this paper, we propose a timing analysis approach for preemptive multi-tasking real-tim...
In this paper, we investigate the problem of inter-task cache interference in preemptive multi-taski...
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap betw...
Schedulability analyses for preemptive real-time systems need to take into account cache-related pre...
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap betw...
Multitasked real-time systems often employ caches to boost performance. However the unpredictable dy...
RAMAPRASAD, HARINI Analytically Bounding Data Cache Behavior for Real-Time Sys-tems. (Under the dire...
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap betw...
In the presence of caches, preemptive scheduling may incur a significant overhead referred to as cac...
Cache locking improves timing predictability at the cost of performance. We explore a novel approach...
23rd IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2017, Pittsburg, PA, US...
Abstract — Schedulability analysis for real-time systems has been the subject of prominent research ...
28th Euromicro Conference on Real-Time Systems (ECRTS 2016). 5 to 8, Jul, 2016. Toulouse, France.Out...
Hard real-time systems are typically composed of multiple tasks, subjected to timing constraints. To...
In this paper, we propose an approach to estimate the Worst Case Response Time (WCRT) of each task i...
Abstract. In this paper, we propose a timing analysis approach for preemptive multi-tasking real-tim...
In this paper, we investigate the problem of inter-task cache interference in preemptive multi-taski...
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap betw...
Schedulability analyses for preemptive real-time systems need to take into account cache-related pre...
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap betw...
Multitasked real-time systems often employ caches to boost performance. However the unpredictable dy...
RAMAPRASAD, HARINI Analytically Bounding Data Cache Behavior for Real-Time Sys-tems. (Under the dire...
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap betw...
In the presence of caches, preemptive scheduling may incur a significant overhead referred to as cac...
Cache locking improves timing predictability at the cost of performance. We explore a novel approach...
23rd IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2017, Pittsburg, PA, US...
Abstract — Schedulability analysis for real-time systems has been the subject of prominent research ...
28th Euromicro Conference on Real-Time Systems (ECRTS 2016). 5 to 8, Jul, 2016. Toulouse, France.Out...
Hard real-time systems are typically composed of multiple tasks, subjected to timing constraints. To...