CABAC : A CCD Clocking and Biasing Chip for LSST Camera

The aim of CABAC, is to provide to the LSST camera CCDs the necessary parallel and serial clocks, the power supply of the output amplifiers (OD) and most of the biases, excluding the HV substrate bias. The LSST focal plane is made of 189 large (4k*4k pixels) and highly segmented (16 outputs) CCDs. Each pixel will be read at a speed of 550kHz for a total readout (3.2 Gpixels) of 2s. To achieve this speed, each CCD will be driven by two CABAC in order to provide the necessary large current to move the 4004 lines of the sensor. CABAC will be implemented on a large REB (Raft Electronics Board) located inside the cryostat, the nominal operating temperature will be -26C. One CABAC is designed to provide : 4 parallel clocks of more than 15V amplitude, rise and fall time of less than 2us on a 66nF capacitive load, and a 8 bit programmable output current capability of 300mA max. 4 serial clocks with more than 15V amplitude, rise and fall time of 60ns on a capacitive load of 300pF, and a 8 bit programmable output current capability of 16mA max. 2 output drains, 8 bit programmable voltage from 13 to 36V with a nominal output current of 16mA each. 3 high level biases, 8 bit programmable from 13 to 36V 2 low level biases, 8 bit programmable from 0 to 5V Finally, for monitoring purpose, an internal dual multiplexer can provide 2 of any CABAC output, including the temperature sensor, and 6 external inputs. A deactivable internal pulser can inject pulse inside the CCD RD (reset drain) allowing electronic calibration of the readout chain. In order to save power during the 15s exposure, CABAC can be put in standby mode. This mode reduces the supply current by a factor of 10 for the clocks circuitry, and can set the OD voltages to a programmable value in order to reduce the glow inside the CCDs. Programation of CABAC is done via a SPI bus. CABAC is designed in CMOS H35 from AMS vendor, encapsulated in a QFN100 package with bottom pad, it is currently under tests