Delay minimization continues to be an important objective in the design of high-performance computing system. In this paper, we present an effective methodology to guide the delay optimization process of the mincut-based global placement via adaptive sequential network characterization. The contribution of this work is the development of a fully automated approach to determine critical parameters related to performance-driven multi-level partitioning-based global placement with retiming. We validate our approach by incorporating this adaptive method into a state-of-the-art global placer GEO. Our A-GEO, the adaptive version of GEO, achieves 67% maximum and 22% average delay improvement over GEO
A novel method, named critical-network-based (CNB), for timing optimization in global routing is pre...
Current placement systems attempt to optimize several objectives, namely area, connection length, an...
Current placement systems attempt to optimize several objectives, namely area, connection length, an...
Delay and wirelength minimization continue to be important objectives in the design of high-performa...
Abstract—In this paper, we formulate the physical planning with retiming problem and propose an algo...
Delay and power minimization are two important objectives in the current circuit designs. Retiming i...
Delay minimization and power minimization are two important objectives in the design of the high-per...
Retiming is a widely investigated technique for performance optimization. In general, it performs ex...
Retiming is a widely investigated technique for performance optimization. It performs powerful modif...
We present a new timing driven method for global placement. Our method is based on the observation t...
With aggressive scaling of semiconductor manufacturing technology in recent decades, the complexity ...
With aggressive scaling of semiconductor manufacturing technology in recent decades, the complexity ...
This thesis presents a comprehensive approach to the VLSI CAD placement problem and proposes several...
Global interconnects are a bottleneck in today's high-performance deep-submicron designs. In this pa...
[[abstract]]We survey recent development in placement technology for VLSI layout. In the very deep s...
A novel method, named critical-network-based (CNB), for timing optimization in global routing is pre...
Current placement systems attempt to optimize several objectives, namely area, connection length, an...
Current placement systems attempt to optimize several objectives, namely area, connection length, an...
Delay and wirelength minimization continue to be important objectives in the design of high-performa...
Abstract—In this paper, we formulate the physical planning with retiming problem and propose an algo...
Delay and power minimization are two important objectives in the current circuit designs. Retiming i...
Delay minimization and power minimization are two important objectives in the design of the high-per...
Retiming is a widely investigated technique for performance optimization. In general, it performs ex...
Retiming is a widely investigated technique for performance optimization. It performs powerful modif...
We present a new timing driven method for global placement. Our method is based on the observation t...
With aggressive scaling of semiconductor manufacturing technology in recent decades, the complexity ...
With aggressive scaling of semiconductor manufacturing technology in recent decades, the complexity ...
This thesis presents a comprehensive approach to the VLSI CAD placement problem and proposes several...
Global interconnects are a bottleneck in today's high-performance deep-submicron designs. In this pa...
[[abstract]]We survey recent development in placement technology for VLSI layout. In the very deep s...
A novel method, named critical-network-based (CNB), for timing optimization in global routing is pre...
Current placement systems attempt to optimize several objectives, namely area, connection length, an...
Current placement systems attempt to optimize several objectives, namely area, connection length, an...