Variation-Aware Energy-Delay Optimization Method for Device/Circuit Co-Design

A new variation-aware energy-delay optimization method is proposed for device-circuit co-design in nanoscale CMOS digital circuits design. Yield is added into traditional energy-delay (ED) optimization method as a figure of merit to take account of ED variation caused by major process variation sources in nanoscale technology. Threshold voltage and supply voltage can be co-optimized to meet any customized energy-delay-yield (EDY) requirements. The efficiency and accuracy of the proposed EDY method is confirmed by circuit simulations targeting at different digital circuit applications. Results from optimization and simulation show great advantage in avoiding over-design compared with the conventional ED method. Furthermore, the extendibility of the proposed method to include reliability-induced degradation and variation is exhibited