High-level estimation and exploration of reliability for multi-processor system-on-chip

Continuous technology scaling in semiconductor industry forces reliability as a serious design concern in the era of nano-scale computing. Traditional device and circuit level reliability estimation and error mitigation techniques neither address the huge design complexity of modern system nor consider architecture and system-level error masking properties. An alternative approach is to accept and expose the unreliability to all layers of computing and possibly mitigate the errors with device-, circuit-, architectural or software techniques. To enable cross-layer exploration of reliability against other performance constraints, it is essential to accurately model the errors in nano-scale technology and develop a smooth tool-flow at high-level design abstractions so that error effects can be estimated, which assists the development of high-level fault-tolerant techniques. In this dissertation, a high-level reliability estimation and exploration framework for MPSoC is developed.To estimate reliability at early design stages, a high-level fault simulation framework is constructed for generic architecture models and integrated into a commercial processor design environment. The fault injector is further extended for system-level modules. A power/thermal/timing error co-simulation framework is demonstrated for integrating fault injection with simulation of physical properties. To further speed up reliability estimation, an analytical method is proposed to calculate vulnerability of individual logic blocks, from which application level error probabilities are deduced. A formal technique is introduced to predict error effects by tracking error propagation. Finally, design diversity metric is utilized to quantify the robustness of redundancy in system-level computing elements.The contributions in reliability exploration include several novel architectural fault-tolerant techniques. Opportunistic redundancy detects errors by re-executing the instructions only if there are underutilized resources. Asymmetric redundancy unequally protects memory elements based on criticality analysis of data and instructions. Error confinement replaces any erroneous result with the best available estimate from statistical characteristics. For system-level fault tolerance, a core reliability-aware task mapping algorithm is demonstrated on a heterogeneous multiprocessor platform. A theoretical approach to construct ad-hoc fault tolerant network for arbitrary task graph with optimal amount of connecting edges is elaborated and verified by exhaustive search based algorithm.The methodologies proposed in this dissertation are going to be critical for future semiconductor technology nodes, where reliability is going to be a permanent problem. Further research directions are outlined to take this research forward