On-chip Interconnect Strategies for Giga-Scale Integration

Today's data-dominated and high-performance applications require the integration of over 1 billion transistors into a single monolithic die. Consequently, the interconnection network that communicates between these transistors is facing an ever-increasing demand to deliver the signals at high-speed, high-bandwidth and low-power dissipation. Process-technology scaling is a key enabler to manufacture high-speed transistors, but this also introduces physical limitations on the performance of the interconnects.This research aims at understanding the impact of the process-technology scaling on the performance of interconnect-dominated chips and at exploring and developing possible application-driven and hierarchy-dependentsolutions to optimize the performance of the interconnection network. In addition, this research also aims at exploring new technology and architecture options to understand the relevant trade-offs that could be exploited to optimize the interconnect performance.This research work is enabled through the application of TAD (Technology-Aware-Design) methodologies which aim at maximizing the synergy between the process-technology domain and system-level design. This is achieved through propagation of the relevant technology information through theuse of accurate models to higher levels. This information flow of accurate technology models to higher levels enables an accurate estimation ofDSM effects in interconnects and also the possible gains in system-level metrics due to exploration of various technology options. The same information flow can be used to optimize the process-technology in an application driven manner.Methodologies developed in this research have shown that a significant performance gain is achievable through application-driven optimization of interconnection network and these results in a better utilization of interconnect resources.status: publishe