Ultra-low-power 130nm SOI CMOS smart sensor for in-situ mechanical stress in SiP and SoC applications

Research motivations: Innovative packaging technologies such as TSV, extreme die thinning or 3D-stacking, lead to new issues regarding mechanical reliability, failure analysis and stress modeling [1] An in-situ SiP or SoC smart stress sensor constitutes a new type of stress conditions monitor, allowing better strategies to avoid overdesigning complex systems [2] Different possibilities are presented to measure the mechanical stress effects of an IC device: -common approach: integrated stress sensitive resistors [3], [4], [5] -alternative approach: bipolar transistors or metal oxide semiconductor transistors [6] Following the alternative approach, we propose an on-chip stress sensitive measurement with complementary MOS (CMOS) sensors and p-channel MOS (PMOS) transistors connected as current mirrors