Serial communication peripheries development in FPGA

This bachelor’s thesis is about two peripheries. First periphery creates from input parallel signals one output serial signal. This serial signal contains a start bit, the next are data bits, parity bit and stop bit or two stop bits. Data bits are variables. It is mean their count is set with two input signals called Dat0 and Dat1. We can secure data bits with parity bit. Of course we have choice between even parity bit or odd parity bit. After parity bit there is one stop bit or there are two stop bits. Second periphery realizes I2C bus. This communication is between two devices. First device is called master and creates the communication with second device called slave. For communication there are two bidirectional lines. The first line is called SDA, which is a serial data line and second line is a serial clock line called SCL. Communication begins with a start condition. That means line SDA go from high to low while SCL is high and communication is terminate with a stop condition. That means line SDA go from low to high while SCL is high. The peripheries are programming in VHDL language and implemented in FPGA device. After successful simulation in free software ISE WebPACK the peripheries was realized in the development board V2MB1000 with device XC2V1000