FPGA-based approach to Level-1 track finding at CMS for the HL-LHC

The high luminosity upgrade of the LHC is expected to deliver luminosities of $7.5 \times 10^{34}$~cm$^{-2}$s$^{-1}$, with an average of 140--200 overlapping proton-proton collisions in each bunch crossing at a frequency of 40~MHz. To maintain manageable trigger rates under these conditions track reconstruction will be incorporated in the all-hardware first level of the CMS trigger. A track-finding algorithm based on seed tracklets has been developed and implemented on commercially available FPGAs for this purpose. An overview of the algorithm is presented, results are shown of its expected performance from simulations, and an implementation of the algorithm in a Xilinix Virtex-7 FPGA for a hardware demonstrator system is discussed