Add to ORKGAbstract The future upgrade of the ATLAS Level-1 Central Trigger will require a new method of control communication to the MUCTPI. IPbus is suggested as a possible solution to this problem and setup instructions are provided. The functionality of IPbus was tested and its performance was measured for different operations and for different parameters. The Hardware Compiler was modified to support IPbus
Forthcoming hardware upgrades to the CMS experiment trigger and readout system are based upon the AT...
Most of the off-detector custom electronics of the ATLAS data acquisition system such as the Read-Ou...
The ATLAS Level-1 Central Trigger (L1CT) consists of the Central Trigger Processor (CTP) and the Muo...
The ATCA and uTCA standards include industry-standard data pathway technologies such as Gigabit Ethe...
The Muon-to-Central Trigger Processor Interface (MUCTPI) of the ATLAS experiment at the Large Hadron...
The Monitoring of the ATLAS Level-1 Central Trigger Operation and its web-based display are describe...
The ATLAS Level-1 (L1) trigger is the first stage of the trigger chain. It must reduce the input dat...
This paper presents an overview of the hardware and software proposed for the ATLAS level 2 Trigger ...
The KEKB Accelerator control system[1] is based on EPICS(Experimental Physics and Industrial Control...
TheAdvancedPhotonSource(APS) control system is based on a distributed topology of microprocessor--ba...
This paper describes an implementation of the high level trigger for the ATLAS experiment on a large...
The Muon to Central Trigger Processor Interface (MUCTPI) of the ATLAS experiment at the Large Hadron...
The Muon to Central Trigger Processor Interface (MUCTPI) of the ATLAS experiment at the Large Hadron...
The Muon-to-Central Trigger Processor Interface (MUCTPI) is part of the Level-1 trigger system of th...
The Muon to Central Trigger Processor Interface (MUCTPI) of the ATLAS experiment at the Large Hadron...
Forthcoming hardware upgrades to the CMS experiment trigger and readout system are based upon the AT...
Most of the off-detector custom electronics of the ATLAS data acquisition system such as the Read-Ou...
The ATLAS Level-1 Central Trigger (L1CT) consists of the Central Trigger Processor (CTP) and the Muo...
The ATCA and uTCA standards include industry-standard data pathway technologies such as Gigabit Ethe...
The Muon-to-Central Trigger Processor Interface (MUCTPI) of the ATLAS experiment at the Large Hadron...
The Monitoring of the ATLAS Level-1 Central Trigger Operation and its web-based display are describe...
The ATLAS Level-1 (L1) trigger is the first stage of the trigger chain. It must reduce the input dat...
This paper presents an overview of the hardware and software proposed for the ATLAS level 2 Trigger ...
The KEKB Accelerator control system[1] is based on EPICS(Experimental Physics and Industrial Control...
TheAdvancedPhotonSource(APS) control system is based on a distributed topology of microprocessor--ba...
This paper describes an implementation of the high level trigger for the ATLAS experiment on a large...
The Muon to Central Trigger Processor Interface (MUCTPI) of the ATLAS experiment at the Large Hadron...
The Muon to Central Trigger Processor Interface (MUCTPI) of the ATLAS experiment at the Large Hadron...
The Muon-to-Central Trigger Processor Interface (MUCTPI) is part of the Level-1 trigger system of th...
The Muon to Central Trigger Processor Interface (MUCTPI) of the ATLAS experiment at the Large Hadron...
Forthcoming hardware upgrades to the CMS experiment trigger and readout system are based upon the AT...
Most of the off-detector custom electronics of the ATLAS data acquisition system such as the Read-Ou...
The ATLAS Level-1 Central Trigger (L1CT) consists of the Central Trigger Processor (CTP) and the Muo...