KLauS – A charge readout and fast discrimination chip for silicon photomultipliers

KLauS is an application specific integrated circuit (ASIC) for the readout of silicon photomultipliers. The chip has been designed for the application in the analog hadronic calorimeter developed by the CALICE collaboration for the next linear collider experiment . To address the severe power constraints introduced by the highly granular design of the calorimeter, the chip has been designed for low power consumption while maintaining the high dynamic range and timing precision required by the experiment. In addition, a power gating scheme has been implemented to further decrease the average power consumption. For a duty cycle of 1% a value of 25µW per channel is achieved without affecting the readout capabilities of the chip. The chip has been designed in the 0.35µm SiGe technology and provides a low power readout channel for SiPMs with low gain for the input stage of the existing readout chip SPIROC. The analog channel of KLauS will be implemented in a future version of the SPIROC chip