Future evolution of the Fast TracKer (FTK) processing unit

The Fast Tracker (FTK) processor [1] for the ATLAS experiment has a computing core made of 128 Processing Units that reconstruct tracks in the silicon detector in a ~100 μsec deep pipeline. The track parameter resolution provided by FTK enables the HLT trigger to identify efficiently and reconstruct significant samples of fermionic Higgs decays. Data processing speed is achieved with custom VLSI pattern recognition, linearized track fitting executed inside modern FPGAs, pipelining, and parallel processing. One large FPGA executes full resolution track fitting inside low resolution candidate tracks found by a set of 16 custom Asic devices, called Associative Memories (AM chips) [2]. The FTK dual structure, based on the cooperation of VLSI dedicated AM and programmable FPGAs, is maintained to achieve further technology performance, miniaturization and integration of the current state of the art prototypes. This allows to fully exploit new applications within and outside the High Energy Physics field. We plan to increase the FPGA parallelism by associating one FPGA to each AM chip. The FPGA configures and handles the AM and provides a flexible computing power to process the shapes selected by the AM. The goals of this new elementary unit made of 2 chips are: maximum parallelism exploitation, low power consumption, execution time at least 1000 times shorter than the best commercial CPUs, distributed debugging and monitoring tools suited for a pipelined, highly parallelized structure, high degree of configurability to face different applications with maximum efficiency