A multi-core FPGA-based 2D-clustering algorithm for real-time image processing is presented. The algorithm uses a moving window technique adjustable to the cluster size in order to minimize the FPGA resources required for cluster identification. The window size is generic and application dependent (size/shape of clusters in the input images). A key element of this algorithm is the possibility to instantiate multiple clustering cores working on different windows that can be used in parallel to increase performance exploiting more resources on the FPGA device. In addition to the offered parallelism, the algorithm is executed in a pipeline, thus allowing the cluster readout to be performed in parallel with the cluster identification and the da...
In this paper, a configurable many-core hardware/ software architecture is proposed to efficiently ...
International audienceField-programmable gate array (FPGAs) are classified as high efficient computa...
In mapping the k-means algorithm to FPGA hardware, we examined algorithm level transforms that drama...
A multi-core FPGA-based 2D-clustering algorithm for real-time image processing is presented. The alg...
A multi-core FPGA-based clustering algorithm for high-throughput data intensive applications is pres...
Real time image analysis has undergone a rapid development in the last few years, due to the increas...
The high performance multi-core 2D pixel clustering FPGA implementation used for the input system of...
The parallel 2D pixel clustering FPGA implementation used for the input system of the ATLAS Fast Tra...
The highly parallel 2D-clustering FPGA implementation used for the input system of Fast TracKer (FTK...
We present a fast general-purpose algorithm for high-throughput clustering of data ”with a two dimen...
K-means clustering has been widely used in processing large datasets in many fields of studies. Adva...
The growing need for smart surveillance solutions requires that modern video capturing devices to be...
Starting from the next LHC run, the upgraded LHCb High Level Trigger will process events at the full...
FPGA-based embedded image processing systems offer considerable computing resources but present prog...
In this paper the performance of the 2D pixel clustering algorithm developed for the Input Mezzanine...
In this paper, a configurable many-core hardware/ software architecture is proposed to efficiently ...
International audienceField-programmable gate array (FPGAs) are classified as high efficient computa...
In mapping the k-means algorithm to FPGA hardware, we examined algorithm level transforms that drama...
A multi-core FPGA-based 2D-clustering algorithm for real-time image processing is presented. The alg...
A multi-core FPGA-based clustering algorithm for high-throughput data intensive applications is pres...
Real time image analysis has undergone a rapid development in the last few years, due to the increas...
The high performance multi-core 2D pixel clustering FPGA implementation used for the input system of...
The parallel 2D pixel clustering FPGA implementation used for the input system of the ATLAS Fast Tra...
The highly parallel 2D-clustering FPGA implementation used for the input system of Fast TracKer (FTK...
We present a fast general-purpose algorithm for high-throughput clustering of data ”with a two dimen...
K-means clustering has been widely used in processing large datasets in many fields of studies. Adva...
The growing need for smart surveillance solutions requires that modern video capturing devices to be...
Starting from the next LHC run, the upgraded LHCb High Level Trigger will process events at the full...
FPGA-based embedded image processing systems offer considerable computing resources but present prog...
In this paper the performance of the 2D pixel clustering algorithm developed for the Input Mezzanine...
In this paper, a configurable many-core hardware/ software architecture is proposed to efficiently ...
International audienceField-programmable gate array (FPGAs) are classified as high efficient computa...
In mapping the k-means algorithm to FPGA hardware, we examined algorithm level transforms that drama...