Design of an FPGA-based embedded system for the ATLAS Tile Calorimeter front-end electronics test-bench

The portable test-bench for the certification of the ATLAS tile hadronic calorimeter front-end electronics has been redesigned for the LHC Long Shutdown (LS1) improving its portability and expanding its functionalities. This paper presents a new test-bench based on a Xilinx Virtex-5 FPGA that implements an embedded system using a hard core PowerPC 440 microprocessor and custom IP cores. A light Linux version runs on the PowerPC microprocessor and handles the IP cores which implement the different functionalities as TTCvi emulation, G-Link decoder ADC control and data reception, needed to perform the desired test