Protecting chips against hold time violations due to variability

With the development of Very-Deep Sub-Micron technologies, process variability is becoming increasingly important and is a very important issue in the design of complex circuits. Process variability is the statistical variation of process parameters, meaning that these parameters do not have always the same value, but become a random variable, with a given mean value and standard deviation. This effect can lead to several issues in digital circuit design.The logical consequence of this parameter variation is that circuit characteristics, as delay and power, also become random variables. BecausThis book presents physical understanding, modeling and simulation, on-chip characterization, layout solutions, and design techniques that are effective to enhance the reliability of various circuit units. The consequences of variability to several aspects of circuit design, such as logic gates, storage elements, clock distribution, and any other that can be affected by process variations are discussed, with a key focus on storage elements. The authors present a statistical analysis of the critical clock skew in several test paths, due to process variability in 130nm and 90nm CMOS technology. To facilitate an on-wafer test, a measurement circuit with a precision compatible to the speed of the technology is described. · Provides a comprehensive review of various reliability mechanisms; · Describes practical modeling and characterization techniques for reliability · Includes thorough presentation of robust design techniques for major VLSI design units · Promotes physical understanding with first-principle simulation