Fast Tracker : A Hardware Real Time Track Finder for the ATLAS Trigger System

The Large Hadron Collider (LHC) after the 2013-­‐2014 shutdown period is expected to improve the yet impressive performance obtained up to this year: collisions’ energy will increase to 14 TeV and instantaneous luminosity will reach and then overcome 10^34 cm‐2s‐1, with a bunch crossing period of 25 ns. The LHC experiments will need to adapt to the more crowded events, maintaining the physics output and the quality of the final results. The pileup higher than the LHC run 1, with peaks expected to reach 50 or more, will make more difficult to have efficient online selection of rare events based mostly on calorimeters and muon detectors as it is done now. A more extensive use of the information collected by the tracking detector will allow building more robust selections, limiting the degradation effects due to the high pileup. We report on the development of the Fast Tracker (FTK) processor for the ATLAS experiment, devoted to reconstruct tracks with transverse momentum above 1 GeV in the whole detector for any event accepted by level 1 trigger. The system is specialized in perform tracking through custom and commercial electronics, using a multistage parallel algorithm. The availability of full tracking for the beginning of second level trigger allows exploiting the ability of tracking to separate pileup events by primary vertex. The FTK make possible new trigger selections, which are robust against pileup. We present recent studies performed for the FTK technical design report (TDR) showing how the possibility to access the full track information at the begin of the level-­‐2 allows improving the performance in many important channels: the identification of hadronic decays coming from tau lepton, using a track-­‐only cone-­‐based algorithm, allows a good efficiency and a sufficient rejection to apply more sophisticated, but also more CPU intensive algorithms to finalize the selection; b-­‐tagging algorithm are also possible, with the capability to have selections with multiple b-­‐tagged jets down to low pT thresholds; additional possibilities are the reconstruction of all the vertexes in the event, the use of track for isolation of muons or electrons. We discuss the design of the system of the parallel pipeline that allows to reconstruct tracks at 100 kHz, reading data received from the whole ATLAS silicon tracker. The system will be in fact composed by about 1000 FPGA, used for reconstruction of pixel clustering, data formatting and track fitting, and more than 16 thousands associative memory (AM) chips. The AM chip had a major technological improvements with the inclusion of the a variable resolution precision in the pattern matching, thanks to the addition the “don’t care” feature introducing ternary cells (0, 1, x) in the AM chip. A global redesign of the AM chip reduces the power consumption, in order to improve the matching perform and allow the construction of very dense boards able to store up to 2^16 patterns per chip and 128 chips per board, totaling about 1 billion patterns for the final system. An innovative ATCA based system has been designed to distribute incoming detector data to 64 parallel track-­‐finding engines (Processing Unit). Within each processing unit there is an additional factor 8 parallelism for a total of 512 pipelines. Within each pipeline a linearized track fit is implemented in a FPGA performing up to 1Gfits/s for a total 0.5Bfits/s