A high speed, low power 16:1 serializer is developed using a commercial 0.25 μm silicon-on-sapphire CMOS technology. It operates from 4.0 to 5.8 Gbps in the lab test. Its total jitter is measured to be 62 ps and the bathtub scan demonstrates a 122 ps opening at BER of less than 10-12 level at 5 Gbps. The measured power consumption is 507 mW at this data rate. A proton test of this chip is scheduled in June and test results will be discussed when available
Based on a commercially available 0.25 µm Silicon on Sapphire CMOS technology, we are developing the...
<p>This data set contains simulation results of a high-speed serializer for a 64 GS s<sup>-1</sup> d...
We present the design and performance of a prototype ASIC digitizer for integrated wire chamber read...
A high speed, low power 16:1 serializer has been developed with a commercial 0.25 μm silicon-on-sapp...
A high speed 16:1 serializer ASIC has been developed using a commercial 0.25 μm silicon-on-sapphire ...
High speed and ultra low power serial data transmission over fiber optics plays an essential roll in...
The current front-end electronics of the ATLAS Liquid Argon calorimeters need to be upgraded to sust...
We have been developing a serializer application-specific integrated circuit (ASIC) based on a comme...
AbstractWe have been developing a serializer application-specific integrated circuit (ASIC) based on...
The extreme particle density in the detectors for high-energy physics experiments set new demands on...
We report on the design of a serializer ASIC to be used in the ATLAS forward muon detector for trigg...
This thesis presents the design and simulation of the schematic of a low-power (5.6pJ/b) dual-mode (...
A new front-end chip (VeloPix) is being developed for the readout of the silicon vertex locator dete...
The multichannel 6-bit ADC ASIC with data serialisation was designed in view of readout sys-tems in ...
Several LHC detectors require high-speed digital optical links for data transmission in both data re...
Based on a commercially available 0.25 µm Silicon on Sapphire CMOS technology, we are developing the...
<p>This data set contains simulation results of a high-speed serializer for a 64 GS s<sup>-1</sup> d...
We present the design and performance of a prototype ASIC digitizer for integrated wire chamber read...
A high speed, low power 16:1 serializer has been developed with a commercial 0.25 μm silicon-on-sapp...
A high speed 16:1 serializer ASIC has been developed using a commercial 0.25 μm silicon-on-sapphire ...
High speed and ultra low power serial data transmission over fiber optics plays an essential roll in...
The current front-end electronics of the ATLAS Liquid Argon calorimeters need to be upgraded to sust...
We have been developing a serializer application-specific integrated circuit (ASIC) based on a comme...
AbstractWe have been developing a serializer application-specific integrated circuit (ASIC) based on...
The extreme particle density in the detectors for high-energy physics experiments set new demands on...
We report on the design of a serializer ASIC to be used in the ATLAS forward muon detector for trigg...
This thesis presents the design and simulation of the schematic of a low-power (5.6pJ/b) dual-mode (...
A new front-end chip (VeloPix) is being developed for the readout of the silicon vertex locator dete...
The multichannel 6-bit ADC ASIC with data serialisation was designed in view of readout sys-tems in ...
Several LHC detectors require high-speed digital optical links for data transmission in both data re...
Based on a commercially available 0.25 µm Silicon on Sapphire CMOS technology, we are developing the...
<p>This data set contains simulation results of a high-speed serializer for a 64 GS s<sup>-1</sup> d...
We present the design and performance of a prototype ASIC digitizer for integrated wire chamber read...