Dynamic Reconfiguration and Incremental Firmware Development in the Xilinx Virtex 5

The size and complexity of the latest generations of FPGAs has increased dramatically. This in turn means that the time taken to develop and build even small firmware projects is increasing exponentially. Pre-constrained logic placement and routing are becoming critically important for the use of specialized components in the FPGA such as serial link interfaces. This necessitates significant changes from 'normal' firmware tool flows in order to effectively develop systems based on these devices. In this paper we discuss several methods for improving turnaround speed and design safety, including: pre-placed and pre-routed hard macros / Relationally Placed Macros (RPMs), and pre-synthesised black-box netlists. Possible methods of dynamic partial reconfiguration are also discussed in this context