Design and measurements of SEU tolerant latches
- Menouni, M
- Arutinov, D
- Barbero, M
- Beccherle, R
- Breugnon, P
- Ely, R
- Fougeron, D
- García-Sciveres, M
- Gnani, D
- Hemperek, T
- Karagounis, M
- Kluit, R
- Mekkaoui, A
- Rozanov, A
- Schipper, J-D
DOIAbstract
Latches based on the Dual Interlocked storage Cell or DICE are very tolerant to Single Event Upsets (SEU). However, for highly scaled processes where the sizes continue to decrease, the data in this latch can be corrupted by an SEU due to charge sharing between adjacent nodes. Some layout considerations are used to improve the tolerance of the DICE latches to SEU and especially the influence of sensitive nodes separation is tested for DICE latches designed with a 130 nm process
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