This brief presents a phase-difference modulation signaling enhanced by decision feedback equalization for multi-drop memory interfaces. The phase-difference modulation signaling enables efficient data communication via a multi-drop channel, but only if the stub lengths are specially engineered. In this brief, the phase-difference modulation signaling is combined with decision feedback equalization to extend the applicable channel range. A test chip with a phase-difference-modulation transmitter and a decision feedback equalization receiver was fabricated in 65-nm CMOS technology. With a 2-tap decision feedback equalization, the test chip achieved the data rate of 7.8 Gb/s/pin via the both multi-drop channels with a long 10-cm stub and a sh...
The signal integrity of dual-rank LPDDR5 interface is challenged by reflections from the stub of the...
Decision feedback equalization (DFE) is a popular technique to counteract inter-symbol interference ...
A 10-Gb/s serial link transceiver is demonstrated using double-edged pulsewidth modulation (DPWM) to...
In this paper, we designed the phase-difference modulation (PDM) transceiver for the application of ...
DoctorThis thesis presents phase-difference-modulation signaling for highly-reflective interconnects...
A 2-Gb/s integrating decision-feedback equalization (DFE) receiver was implemented for a four-drop s...
In this contribution, we present a multiple-input multiple-output (MIMO) equalizer with decision fee...
A guideline on how to design and specify a Decision Feedback Equalizer (DFE) for bitrates of 10 Gbps...
The proposed 2 post-tap decision feedback equalizer (DFE) implementation consists of two equalizing ...
A novel analog decision-feedback equalizer (ADFE) is presented to compensate for modal dispersion in...
A current-mode differential signaling of three data over two pairs of transmission lines increases t...
This brief presents a high-speed inductorless D flipflop (DFF) architecture that works on the princi...
Abstract—This paper presents a 90-nm CMOS 10-Gb/s trans-ceiver for chip-to-chip communications. To m...
Decision feedback equalizers (DFEs) play a critical role in high-speed communications through band-...
Multi-tap decision-feedback-equalization (DFE) is proposed to counteract inter-symbol interference (...
The signal integrity of dual-rank LPDDR5 interface is challenged by reflections from the stub of the...
Decision feedback equalization (DFE) is a popular technique to counteract inter-symbol interference ...
A 10-Gb/s serial link transceiver is demonstrated using double-edged pulsewidth modulation (DPWM) to...
In this paper, we designed the phase-difference modulation (PDM) transceiver for the application of ...
DoctorThis thesis presents phase-difference-modulation signaling for highly-reflective interconnects...
A 2-Gb/s integrating decision-feedback equalization (DFE) receiver was implemented for a four-drop s...
In this contribution, we present a multiple-input multiple-output (MIMO) equalizer with decision fee...
A guideline on how to design and specify a Decision Feedback Equalizer (DFE) for bitrates of 10 Gbps...
The proposed 2 post-tap decision feedback equalizer (DFE) implementation consists of two equalizing ...
A novel analog decision-feedback equalizer (ADFE) is presented to compensate for modal dispersion in...
A current-mode differential signaling of three data over two pairs of transmission lines increases t...
This brief presents a high-speed inductorless D flipflop (DFF) architecture that works on the princi...
Abstract—This paper presents a 90-nm CMOS 10-Gb/s trans-ceiver for chip-to-chip communications. To m...
Decision feedback equalizers (DFEs) play a critical role in high-speed communications through band-...
Multi-tap decision-feedback-equalization (DFE) is proposed to counteract inter-symbol interference (...
The signal integrity of dual-rank LPDDR5 interface is challenged by reflections from the stub of the...
Decision feedback equalization (DFE) is a popular technique to counteract inter-symbol interference ...
A 10-Gb/s serial link transceiver is demonstrated using double-edged pulsewidth modulation (DPWM) to...