Digital Signal Processing for the Multi-Bunch LHC Transverse Feedback System

For the LHC a VME card has been developed that contains all functionalities for transverse damping, diagnostics and controlled bunch by bunch excitation. It receives the normalized bunch by bunch position from two pick-ups via Gigabit Serial Links (SERDES). A Stratix II FPGA is responsible for resynchronising the two data streams to the bunch-synchronous clock domain (40.08 MHz) and then applying all the digital signal processing: In addition to the classic functionalities (gain balance, rejection of closed orbit, pick-up combinations, one-turn delay) it contains 3- turn Hilbert filters for phase adjustment with a single pickup scheme, a phase equalizer to correct for the non-linear phase response of the power amplifier and an interpolator to double the processing frequency followed by a low-pass filter to precisely control the bandwidth. Using two clock domains in the FPGA the phase of the feedback loop can be adjusted with a resolution of 10 ps. Built-in diagnostic memory (observation and post-mortem) and excitation memory for setting-up are also included. The card receives functions to continuously adjust its parameters as required during injection, ramping and physics