An optical data receiver for integrated photonic interconnects

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.Cataloged from PDF version of thesis.Includes bibliographical references (p. 91-92).The throughput bounds of traditional interconnect networks in microprocessors are being pushed to their limits. In past single-core processors, the number of long global wires constituted only a small fraction of the total. However, with the emergence of multi-core systems, where each core must be able to communicate with each other as well as off-chip memory, global interconnects have become a major bottleneck. The solution has been proposed through integrated photonic networks, where multiple channels of information can be placed onto a single low-latency waveguide, reducing the number of interconnects and increasing the speed of transmission. This work presents a novel optical data receiver for integrated optical links. Both the optical receiver and the photodiode are monolithically-integrated in the same CMOS substrate. The highly-digital receiver senses the photodiode current using a regenerative cross-coupled latch. The photodiode is modelled as an ideal current source with a capacitance in parallel. The receiver operates in two phases, receiving one bit per clock cycle, and is able to resolve input photocurrents of less than 50,PA at 5-Gb/s with a power consumption of less than 500yW (100fJ/bit). The receiver was fabricated in a 32-nm CMOS process as part of a flexible test vehicle that will demonstrate various optical components and the electronic systems that interface with them.by Michael S. Georgas.S.M