LHC technological challenges: use of digital signal processors in the power converters for the LHC particle accelerator

The Large Hadron Collider (LHC) is the next accelerator being constructed on the CERN site. It will be installed in a 27 km circumference tunnel, about 100 m underground. The LHC design is based on superconducting magnets (up to 9 T) which operate in a superfluid helium bath at 1.9 K. This machine is scheduled to come into operation in 2008. In all, there will be 1720 power converters having a total steady-state input power of 63 MW and a peak power of 86 MW. They will supply a total current of about 1850 kA and are, in general, characterized by having high current (up to 20 kA) and low voltage with very high precision. We describe the main components of the LHC powering and their challenges. The performance, design constraints, and topologies of the power converters will be presented. We discuss in detail the use of CERN-designed digital signal processor boards with the main emphasis being on the control loop design