Design of on-chip data sparsification for a mixed-mode MAPS device

The device described in the paper is built up of a bidimensional matrix of Monolithic Active Pixel Sensor (MAPS) and an off-pixel digital readout sparsification circuit. The readout logic is based on std-cells and implements an optimised technique aimed at overcoming the readout speed limit of future large-matrix pixel detectors for particle tracking, by matching the requirements of future HEP experiments. In particular, the readout architecture extends the flexibility of the MAPS devices to be also used in first level triggers in vertex detectors. The work extends a first version of a mixed mode device submitted on Nov. 2006 and implemented with the same technology