Add to ORKGThesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1998.Includes bibliographical references (leaves 60-63).by Michael Sung.M.Eng
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Compute...
We explore the use of compiler optimizations, which optimize the layout of instructions in memory. T...
This dissertation addresses two sets of challenges facing processor design as the industry enters th...
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Compute...
Techniques such as out-of-order issue and speculative execution aggressively exploit instruction lev...
To maximize the performance of a wide-issue superscalar processor, the fetch mechanism must be capab...
This thesis evaluates an innovative cache design called, prime-mapped cache. The performance analysi...
As the instruction issue width of superscalar proces-sors increases, instruction fetch bandwidth req...
The Software Trace Cache is a compiler transformation, or a postcompilation binary optimization, tha...
In superscalar processors, capable of issuing and executing multiple instructions per cycle, fetch p...
As the issue width of superscalar processors is increased, instruction fetch bandwidth requirements ...
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer S...
The processor-memory gap is widening every year with no prospect of reprieve. More and more latency ...
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer S...
Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer ...
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Compute...
We explore the use of compiler optimizations, which optimize the layout of instructions in memory. T...
This dissertation addresses two sets of challenges facing processor design as the industry enters th...
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Compute...
Techniques such as out-of-order issue and speculative execution aggressively exploit instruction lev...
To maximize the performance of a wide-issue superscalar processor, the fetch mechanism must be capab...
This thesis evaluates an innovative cache design called, prime-mapped cache. The performance analysi...
As the instruction issue width of superscalar proces-sors increases, instruction fetch bandwidth req...
The Software Trace Cache is a compiler transformation, or a postcompilation binary optimization, tha...
In superscalar processors, capable of issuing and executing multiple instructions per cycle, fetch p...
As the issue width of superscalar processors is increased, instruction fetch bandwidth requirements ...
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer S...
The processor-memory gap is widening every year with no prospect of reprieve. More and more latency ...
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer S...
Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer ...
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Compute...
We explore the use of compiler optimizations, which optimize the layout of instructions in memory. T...
This dissertation addresses two sets of challenges facing processor design as the industry enters th...