Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.Includes bibliographical references (p. 91-92).In this thesis, we present the framework for Rapid Protocol Engine Development (RaPED). We implemented the framework in Bluespec, which is a high level hardware language based on Term Rewriting Systems (TRSs). The framework is highly parameterized and general, thus allowing designers to design any protocol engine in a short period. Since protocol engines can be developed rapidly, designers can compare different designs instead of freezing the design prematurely in the development process. We used the RaPED to implement a cache coherence protocol for Shen and Arvind's Commit-Reconcile...
Due to VLSI lithography problems and the limitation of additional architectural enhancements uniproc...
International audienceTo facilitate programming, most multi-core processors feature automated mechan...
As the number of NUMA system\u27s cache coherency protocols based on the IEEE Std. 1596-1992, Standa...
In this paper we describe our experience with Teapot [7], a domain-specific language for writing cac...
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer S...
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer S...
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Compute...
Design complexity and limited power budget are causing the number of cores on the same chip to grow ...
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Compute...
In this paper, we describe Teapot, a domain-specific language for writing cache coherence protocols....
Caches have the potential to provide multiprocessors with an automatic mechanism for reducing both n...
Cache coherence is one of the main challenges to tackle when designing a shared-memory multiprocesso...
Number of cores in multi-core processors is steadily increased to make it faster and more reliable. ...
Cache coherency is crucial to multi-core systems with a shared memory programming model. Coherency p...
There are few published examples of the proof of correctness of a cache-coherence protocol expressed...
Due to VLSI lithography problems and the limitation of additional architectural enhancements uniproc...
International audienceTo facilitate programming, most multi-core processors feature automated mechan...
As the number of NUMA system\u27s cache coherency protocols based on the IEEE Std. 1596-1992, Standa...
In this paper we describe our experience with Teapot [7], a domain-specific language for writing cac...
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer S...
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer S...
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Compute...
Design complexity and limited power budget are causing the number of cores on the same chip to grow ...
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Compute...
In this paper, we describe Teapot, a domain-specific language for writing cache coherence protocols....
Caches have the potential to provide multiprocessors with an automatic mechanism for reducing both n...
Cache coherence is one of the main challenges to tackle when designing a shared-memory multiprocesso...
Number of cores in multi-core processors is steadily increased to make it faster and more reliable. ...
Cache coherency is crucial to multi-core systems with a shared memory programming model. Coherency p...
There are few published examples of the proof of correctness of a cache-coherence protocol expressed...
Due to VLSI lithography problems and the limitation of additional architectural enhancements uniproc...
International audienceTo facilitate programming, most multi-core processors feature automated mechan...
As the number of NUMA system\u27s cache coherency protocols based on the IEEE Std. 1596-1992, Standa...