Building custom processors with Handel-C

Triggering and data acquisition for the ATLAS LHC experiment requires state of the art computer hardware. Amongst other things, specialised processors may be required. To build these economically we are looking at reconfigurable computing, and a high-level hardware description language: Handel-C. We had previously implemented a specialised network hardware application in AHDL-a hardware description at the level of gates, flip-flops and state machines. As a feasibility study, we have rewritten the application in Handel-C -a language similar to C, except that it can be translated into hardware. There were problems to solve: high data throughput with complex pipelines; timing constraints; I/O interfaces to external devices; difficulties with the Altera devices. We gained valuable experience, wrote useful support tools, and discovered clean new ways to make the most of the language in the high-speed domain. (0 refs)