Mechanics, mechanisms, and modeling of the chemical mechanical polishing process

Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Mechanical Engineering, 2001.Includes bibliographical references.The ever-increasing demand for high-performance microelectronic devices has motivated the semiconductor industry to design and manufacture Ultra-Large-Scale Integrated (ULSI) circuits with smaller feature size, higher resolution, denser packing, and multi-layer interconnects. The ULSI technology places stringent demands on global planarity of the Interlevel Dielectric (ILD) layers. Compared with other planarization techniques, the Chemical Mechanical Polishing (CMP) process produces excellent local and global planarization at low cost. It is thus widely adopted for planarizing inter-level dielectric (silicon dioxide) layers. Moreover, CMP is a critical process for fabricating the Cu damascene patterns, low-k dielectrics, and shallow isolated trenches. The wide range of materials to be polished concurrently or sequentially, however, increases the complexity of CMP and necessitates an understanding of the process fundamentals for optimal process design. This thesis establishes a theoretical framework to relate the process parameters to the different wafer/pad contact modes to study the behavior of wafer-scale polishing. Several models of polishing - microcutting, brittle fracture, surface melting and burnishing - are reviewed. Blanket wafers coated with a wide range of materials are polished to verify the models. Plastic deformation is identified as the dominant mechanism of material removal in fine abrasive polishing.(cont.) Additionally, contact mechanics models, which relate the pressure distribution to the pattern geometry and pad elastic properties, explain the die-scale variation of material removal rate (MRR) on pattern geometry. The pad displacement into low features of submicron lines is less than 0.1 nm. Hence the applied load is only carried by the high features, and the pressure on high features increases with the area fraction of interconnects. Experiments study the effects of pattern geometry on the rates of pattern planarization, oxide overpolishing and Cu dishing. It was observed that Cu dishing of submicron features is less than 20 nm and contributes less to surface non-uniformity than does oxide overpolishing. Finally, a novel in situ detection technique, based on the change of the reflectance of the patterned surface at different polishing stages, is developed to detect the process endpoint and minimize overpolishing. Models that employ light scattering theory and statistical treatment correlate the sampled reflectance with the surface topography and Cu area fraction for detecting the process regime and endpoint. The experimental results agree well with the endpoint detection schemes predicted by the models.by Jiun-Yu Lai.Ph.D