Scheduling tasks to efficiently use the available processor resources is crucial to minimizing the runtime of applications on shared-memory parallel processors. One factor that contributes to poor processor utilization is the idle time caused by long latency operations, such as remote memory references or processor synchronization operations. One way of tolerating this latency is to use a processor with multiple hardware contexts that can rapidly switch to executing another thread of computation whenever a long latency operation occurs, thus increasing processor utilization by overlapping computation with communication. Although multiple contexts are effective for tolerating latency, this effectiveness can be limited by mem...
Cache utilisation is often very poor in multithreaded applications, due to the loss of data access l...
Multithreading techniques used within computer processors aim to provide the computer system with ...
Chip-level multiprocessors (CMP) have multiple processing cores (Cores) and generally have their cac...
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer...
Thread level parallelism of applications is commonly exploited using multi-thread processors. In suc...
Simultaneous multithreading (SMT) allows multiple hardware threads to execute concurrently on a proc...
Multithreading has emerged as a leading paradigm for the development of applications with demanding ...
The full potential of chip multiprocessors remains unex- ploited due to the thread oblivious memory ...
This paper describes a method to improve the cache locality of sequential programs by scheduling fin...
The era of multi-core processors has begun. These multi- core processors represent a significant shi...
Modern computers have many CPU cores, but unless the problem to be solved is highly parallel, these ...
A modern high-performance multi-core processor has large shared cache memories. However, simultaneou...
Exploitation of parallelism has for decades been central to the pursuit of computing performance. Th...
In this dissertation we present a methodology for predicting the best priority pair for a given co-s...
We present a new operating system scheduling algorithm for multicore processors. Our algorithm reduc...
Cache utilisation is often very poor in multithreaded applications, due to the loss of data access l...
Multithreading techniques used within computer processors aim to provide the computer system with ...
Chip-level multiprocessors (CMP) have multiple processing cores (Cores) and generally have their cac...
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer...
Thread level parallelism of applications is commonly exploited using multi-thread processors. In suc...
Simultaneous multithreading (SMT) allows multiple hardware threads to execute concurrently on a proc...
Multithreading has emerged as a leading paradigm for the development of applications with demanding ...
The full potential of chip multiprocessors remains unex- ploited due to the thread oblivious memory ...
This paper describes a method to improve the cache locality of sequential programs by scheduling fin...
The era of multi-core processors has begun. These multi- core processors represent a significant shi...
Modern computers have many CPU cores, but unless the problem to be solved is highly parallel, these ...
A modern high-performance multi-core processor has large shared cache memories. However, simultaneou...
Exploitation of parallelism has for decades been central to the pursuit of computing performance. Th...
In this dissertation we present a methodology for predicting the best priority pair for a given co-s...
We present a new operating system scheduling algorithm for multicore processors. Our algorithm reduc...
Cache utilisation is often very poor in multithreaded applications, due to the loss of data access l...
Multithreading techniques used within computer processors aim to provide the computer system with ...
Chip-level multiprocessors (CMP) have multiple processing cores (Cores) and generally have their cac...