Add to ORKGOriginally presented as author's thesis (Electrical Engineer --Massachusetts Institute of Technology) 1985.Bibliography: leaf 116.Supported in part by the U.S. Air Force Office of Scientific Research contract F49620-84-C-0004Robert Clyde Armstrong
This thesis presents a versatile new multiplier architecture, which can provide better performance t...
The main contribution of this thesis is the successful development of a vector floating point proces...
There is a huge demand in high speed arithmetic blocks, due to increased performance of processing u...
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Compute...
Originally presented as author's thesis (M.S.--Massachusetts Institute of Technology), 1985.Bibliogr...
Contains report on one research project.U.S. Air Force - Office of Scientific Research (Contract F49...
A 16 bit floating point (FP) Arithmetic Logic Unit (ALU) was designed and implemented in 0.35µm CMOS...
High speed computation is the need of today’s generation of Processors. To accomplish this major tas...
A floating-point unit (FPU) colloquially is a math coprocessor, which is a part of a computer system...
ECTI TRANSACTIONS ON COMPUTER AND INFORMATION TECHNOLOGY, VOL.6, NO.1 May 2012This paper presents th...
Many computationally intensive scientific applications involve repetitive floating point operations ...
This work presents a new fast and efficient algorithm for a floating point multiplier that adheres t...
The challenge in designing a floating-point arithmetic co-processor/processor for scientific and eng...
Floating-point numbers are broadly received in numerous applications due their element representatio...
Title also in Chinese.Thesis (M.Phil.)--Chinese University of Hong Kong.Bibliography: leaves 159-161
This thesis presents a versatile new multiplier architecture, which can provide better performance t...
The main contribution of this thesis is the successful development of a vector floating point proces...
There is a huge demand in high speed arithmetic blocks, due to increased performance of processing u...
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Compute...
Originally presented as author's thesis (M.S.--Massachusetts Institute of Technology), 1985.Bibliogr...
Contains report on one research project.U.S. Air Force - Office of Scientific Research (Contract F49...
A 16 bit floating point (FP) Arithmetic Logic Unit (ALU) was designed and implemented in 0.35µm CMOS...
High speed computation is the need of today’s generation of Processors. To accomplish this major tas...
A floating-point unit (FPU) colloquially is a math coprocessor, which is a part of a computer system...
ECTI TRANSACTIONS ON COMPUTER AND INFORMATION TECHNOLOGY, VOL.6, NO.1 May 2012This paper presents th...
Many computationally intensive scientific applications involve repetitive floating point operations ...
This work presents a new fast and efficient algorithm for a floating point multiplier that adheres t...
The challenge in designing a floating-point arithmetic co-processor/processor for scientific and eng...
Floating-point numbers are broadly received in numerous applications due their element representatio...
Title also in Chinese.Thesis (M.Phil.)--Chinese University of Hong Kong.Bibliography: leaves 159-161
This thesis presents a versatile new multiplier architecture, which can provide better performance t...
The main contribution of this thesis is the successful development of a vector floating point proces...
There is a huge demand in high speed arithmetic blocks, due to increased performance of processing u...