Modeling with logical time in UML for real-time embedded system design

Design of real-time embedded systems requires particular attention to the careful scheduling of application onto execution platform. Precise cycle allocation is often requested to obtain full communication and computation throughput. Our objective is to provide a UML profile where events, actions, and objects can be annotated by ``logical'' clocks. Initially, clocks are not necessarily related. The goal of the scheduling process (and algorithms) is to regulate the data and control flows within predictable bounds. To this end it extracts clock relations that best map the application onto a desired execution platform. ``Clocks-as-schedules'' then act as activation conditions, driving these internal events and actions according to the desired activation patterns. Extra communication and buffering latencies can be introduced in the process. In the paper we describe the domain view of multiple time and logical clocks. We introduce a range of useful operations on them, and their use in various UML views