Add to ORKGWe present a method for generating an interface between an architecture executing a regular program and a host processor, during an hardware-software co-design process. The interface is generated by static analysis of a single assignment Alfa program and of its scheduling. This method is implement- ed in the MMAlpha design environment, and was experimented on a H261 image coder
The design of an instruction set processor includes several related design tasks: instruction set de...
In a parallel programming environment, the load sharing module - or application level scheduler - ma...
Several system-on-chip (SoC) platforms have recently emerged that use reconfigurable logic (FPGAs) a...
We present a method for generating an interface between an architecture executing a regular program ...
Theme 1 - Reseaux et systemes. Projet CosiSIGLEAvailable from INIST (FR), Document Supply Service, u...
The paper introduces a software architecture to support a user from the image processing community i...
In this paper, the problem of automatically mapping large-grain dataflow programs onto heterogeneous...
International audienceThis paper presents a new development of rapid prototyping tools for system de...
Programming applications in computer aided design of VLSI is difficult on parallel architectures, es...
Abstract—Hardware accelerators are widely adopted to speed up computationally onerous applications. ...
The growing complexity of digital signal processing applications make a compelling case the use of h...
Functional dataflow programming languages are designed to create parallel portable programs. The sou...
Development of multimedia systems that can be targeted to different platforms is challenging due to ...
Whether for use as the final target or simply a rapid prototyping platform, programming systems cont...
The growing complexity of digital signal processing applications make a compelling case the use of h...
The design of an instruction set processor includes several related design tasks: instruction set de...
In a parallel programming environment, the load sharing module - or application level scheduler - ma...
Several system-on-chip (SoC) platforms have recently emerged that use reconfigurable logic (FPGAs) a...
We present a method for generating an interface between an architecture executing a regular program ...
Theme 1 - Reseaux et systemes. Projet CosiSIGLEAvailable from INIST (FR), Document Supply Service, u...
The paper introduces a software architecture to support a user from the image processing community i...
In this paper, the problem of automatically mapping large-grain dataflow programs onto heterogeneous...
International audienceThis paper presents a new development of rapid prototyping tools for system de...
Programming applications in computer aided design of VLSI is difficult on parallel architectures, es...
Abstract—Hardware accelerators are widely adopted to speed up computationally onerous applications. ...
The growing complexity of digital signal processing applications make a compelling case the use of h...
Functional dataflow programming languages are designed to create parallel portable programs. The sou...
Development of multimedia systems that can be targeted to different platforms is challenging due to ...
Whether for use as the final target or simply a rapid prototyping platform, programming systems cont...
The growing complexity of digital signal processing applications make a compelling case the use of h...
The design of an instruction set processor includes several related design tasks: instruction set de...
In a parallel programming environment, the load sharing module - or application level scheduler - ma...
Several system-on-chip (SoC) platforms have recently emerged that use reconfigurable logic (FPGAs) a...