Add to ORKGMost newly announced microprocessors manipulate 64-bit virtual addresses and the width of physical addresses is also growing. As a result, the relative size of the address tags in the L1 cache is increasing. This is particularly dramatic when small block sizes are used. At the same time, the performance of complex superscalar processors depends more and more on the accuracy of branch prediction, while the size of the Branch Target Buffer is also increasing linearly with the address width. In this paper, we apply the very simple principle enounced in the title for limiting the tag size of on-chip caches, and for limiting the size of the Branch Target Buffer. In an indirect-tagged cache, the anachronic duplication of the page number in proces...
On-chip caches have been playing an important role in achieving high performance processors. In part...
We propose a novel energy-efficient memory architecture which relies on the use of cache with a redu...
Abstract: Caches contribute to much of a microprocessor system's set-associative cache. However...
Most newly announced microprocessors manipulate 64-bit virtual addresses and the width of physical a...
Most newly announced high erformance micro ro-/ {cessors sup ort 64-bit virtual ad resses and the wi...
This paper presents a technique for minimizing chip-area cost of implementing an on-chip cache memor...
This paper presents a technique for minimizing chip-area cost of implementing an on-chip cache memor...
In current processors, the cache controller, which contains the cache directory and other logic such...
Many contemporary applications feature multi-megabyte instruction footprints that overwhelm the capa...
We revisit the idea of using small line buffers in-front of caches. We propose ReCast, a tiny tag se...
Sectored caches have been used for many years in order to reduce the tag volume needed in a cache. I...
This paper proposes an architecture for low-power direct-mapped instruction caches, called “history-...
We characterize the cache behavior of an in-memory tag table and demonstrate that an optimized imple...
Achieving high instruction issue rates depends on the ability to dynamically predict branches. We co...
Processor architectures will increasingly rely on issuing multiple instructions to make full use of ...
On-chip caches have been playing an important role in achieving high performance processors. In part...
We propose a novel energy-efficient memory architecture which relies on the use of cache with a redu...
Abstract: Caches contribute to much of a microprocessor system's set-associative cache. However...
Most newly announced microprocessors manipulate 64-bit virtual addresses and the width of physical a...
Most newly announced high erformance micro ro-/ {cessors sup ort 64-bit virtual ad resses and the wi...
This paper presents a technique for minimizing chip-area cost of implementing an on-chip cache memor...
This paper presents a technique for minimizing chip-area cost of implementing an on-chip cache memor...
In current processors, the cache controller, which contains the cache directory and other logic such...
Many contemporary applications feature multi-megabyte instruction footprints that overwhelm the capa...
We revisit the idea of using small line buffers in-front of caches. We propose ReCast, a tiny tag se...
Sectored caches have been used for many years in order to reduce the tag volume needed in a cache. I...
This paper proposes an architecture for low-power direct-mapped instruction caches, called “history-...
We characterize the cache behavior of an in-memory tag table and demonstrate that an optimized imple...
Achieving high instruction issue rates depends on the ability to dynamically predict branches. We co...
Processor architectures will increasingly rely on issuing multiple instructions to make full use of ...
On-chip caches have been playing an important role in achieving high performance processors. In part...
We propose a novel energy-efficient memory architecture which relies on the use of cache with a redu...
Abstract: Caches contribute to much of a microprocessor system's set-associative cache. However...