Design of an 8x8 Intra Prediction Module

In this thesis, a proposed hardware architecture of an H.264/AVC 8 × 8luminance intra prediction module is designed and realized in VHDL tobe used on an FPGA. The module is a part of a MPEG-2 to H.264/AVCtranscoder and its implementation is based on an existing design of a4 × 4 luminance intra prediction module used in the same transcoder.Intra prediction is characterized by high data dependency betweeninput video frames which makes it hard to achieve a high throughput. Thisis solved by processing 16 image samples in parallel and by implementinga partial pipeline to increase efficiency.The design is implemented and synthesized on the Kintex-7 XC7K325Tboard with a maximum clock frequency of 129.34 MHz, which gives athroughput of 456.32 Mpixels/s. This is enough to encode 2160p (4kUHD) video frames at 30 frames per second in real time