AbstractArchitecture specifications such as Armv8-A and RISC-V are the ultimate foundation for software verification and the correctness criteria for hardware verification. They should define the allowed sequential and relaxed-memory concurrency behaviour of programs, but hitherto there has been no integration of full-scale instruction-set architecture (ISA) semantics with axiomatic concurrency models, either in mathematics or in tools. These ISA semantics can be surprisingly large and intricate, e.g. 100k+ lines for Armv8-A. In this paper we present a tool, Isla, for computing the allowed behaviours of concurrent litmus tests with respect to full-scale ISA definitions, in Sail, and arbitrary axiomatic relaxed-memory concurrency models, i...
Machine-readable specifications for the Armv8 instruction set architecture have become publicly avai...
ARM has a relaxed memory model, previously specified in informal prose for ARMv7 and AR...
To improve efficiency of memory accesses, modern multiprocessor architectures implement a whole rang...
Copyright is held by the owner/author(s). In this paper we develop semantics for key aspects of the ...
International audienceIn this paper we develop semantics for key aspects of the ARMv8 multiprocessor...
This work was partly funded by the EPSRC Programme Grant REMS: Rigorous Engineering for Mainstream S...
Architecture specifications notionally define the fundamental interface between hardware and softwar...
AbstractComputing relies on architecture specifications to decouple hardware and software developmen...
International audienceComputing relies on architecture specifications to decouple hardware and softw...
International audienceWe report on the process for formal concurrency modelling at Arm. An initial f...
© 2019 Copyright held by the owner/author(s). Publication rights licensed to ACM.For ARMv8 and RISC-...
Virtual memory is an essential mechanism for enforcing security boundaries, but its relaxed-memory c...
ARM has a relaxed memory model, previously specified in informal prose for ARMv7 and ARMv8. Over tim...
Weakly consistent multiprocessors such as ARM and IBM POWER have been with us for decades, but their...
ARM has a relaxed memory model, previously specified in informal prose for ARMv7 and ARMv8. Over tim...
Machine-readable specifications for the Armv8 instruction set architecture have become publicly avai...
ARM has a relaxed memory model, previously specified in informal prose for ARMv7 and AR...
To improve efficiency of memory accesses, modern multiprocessor architectures implement a whole rang...
Copyright is held by the owner/author(s). In this paper we develop semantics for key aspects of the ...
International audienceIn this paper we develop semantics for key aspects of the ARMv8 multiprocessor...
This work was partly funded by the EPSRC Programme Grant REMS: Rigorous Engineering for Mainstream S...
Architecture specifications notionally define the fundamental interface between hardware and softwar...
AbstractComputing relies on architecture specifications to decouple hardware and software developmen...
International audienceComputing relies on architecture specifications to decouple hardware and softw...
International audienceWe report on the process for formal concurrency modelling at Arm. An initial f...
© 2019 Copyright held by the owner/author(s). Publication rights licensed to ACM.For ARMv8 and RISC-...
Virtual memory is an essential mechanism for enforcing security boundaries, but its relaxed-memory c...
ARM has a relaxed memory model, previously specified in informal prose for ARMv7 and ARMv8. Over tim...
Weakly consistent multiprocessors such as ARM and IBM POWER have been with us for decades, but their...
ARM has a relaxed memory model, previously specified in informal prose for ARMv7 and ARMv8. Over tim...
Machine-readable specifications for the Armv8 instruction set architecture have become publicly avai...
ARM has a relaxed memory model, previously specified in informal prose for ARMv7 and AR...
To improve efficiency of memory accesses, modern multiprocessor architectures implement a whole rang...