Robust Acceleration of Data-Centric Applications using Resistive Computing Systems

With the accessible data reaching zettabyte level, CMOS technology is reaching its limit for the data hungry applications. Moore\u27s law has been reaching its depletion in recent studies. On the other hand, von Neumann architecture is approaching the bottleneck due to the data movement between the computing and memory units. With data movement and power budgets becoming the limiting factors of today\u27s computing systems, in-memory computing using emerging non-volatile resistive devices has attracted an increasing amount of attention. A non-volatile resistive device may be realized using memristor, resistive random access memory (ReRAM), phase change memory (PCM), or spin-transfer torque magnetic random access memory (STT-MRAM). Resistive devices integrated into crossbar arrays simultaneously supports both dense storage and energy-efficient analog computation, which is highly desirable for processing of big data using both low-power mobile devices and high-performance computing (HPC) systems. However, analog computation is vulnerable and may suffer from robustness issues due to variations such as, array parasitics, device defects, non-ideal device characteristics, and various sources of errors. These non-ideal factors directly impact the computational accuracy of the in-memory computation and thereby the application level functional correctness. This dissertation is focused on improving the robustness and reliability of analog in-memory computing. Three directions are mainly explored: data layout organization techniques, software and hardware co-design, and hardware redundancy. Data layout organization aims to improve the robustness by masking the data to hardware according to the behavior of defective devices. Software and hardware co-design mitigates the impact by modifying the data in the neural networks or image compression applications to become amenable to device defects and data layout organizations. Hardware redundancy utilized multiple resistive device to realize each data, so each device can be programmed with different value and realize the data accurately with lower overhead