VHDL implementation of reduced complexity Wallace multiplier and performance analysis comparison

One of the most important core components for arithmetic operations in a digital system is a multiplier. The overall performance of a multiplier is dependent on adder performance. Wallace multiplier is one of first approaches to improve the performance of the traditional multiplier operation. After that, many modified approaches were proposed to improve the performance of Wallace multiplier and the other types of multipliers. Various types of adders are used to design the enhanced Wallace tree multiplier. One of the very recent introduced full adder is called energy efficient CMOS full adder (EECFA). The research area for improving overall multiplier performances is vast and the three most important matrices to determine the performance of a multiplier are area, speed and power dissipation. In this thesis, one of the most recently proposed, the reduced complexity Wallace multiplier using energy efficient CMOS full adder was implemented using the VHSIC Hardware Description Language and then a comparative performance analysis with the conventional Wallace Multiplier and Dadda Multiplier is presented in terms of area, speed and power dissipatio