Configurable version management hardware transactional memory for embedded multiprocessor field-programmable gate array

Multiprocessor platforms have been introduced to solve the performance limitation of uni-processor platform. However, programming on a shared memory multiprocessor platform in an efficient way is difficult. The inefficiency of lock based synchronization limits the performance of the parallel programs. Transactional memory (TM) provides a promising method in creating an abstraction layer for programmers to maximize hardware capacity of multiprocessor platform. Hardware TM (HTM) is faster compared to software TM although the performance of hardware transactional memory (HTM) is application-specific. Previous HTM implementations for embedded system were built on fixed version management which results in significant performance loss when transaction behaviour changes. In this thesis, a configurable version management HTM is proposed. The proposed version management is able to be configured to eager version management for low contention applications since it allows fast commit, or lazy version management that is suitable for applications with high contention since it can abort fast. In this work, an analytical model of the proposed hardware transactional processing time for different version management has been developed. With the analytical model, the bounds of the worst case and best case processing time can be estimated for a particular transaction size. The switching point of the performance between eager and lazy version management can also be estimated. The HTM has been prototyped and analyzed on Altera Cyclone IV platform. Based on our experiments, lazy version management is able to obtain up to 12.82% speed-up while eager version management obtains up to 37.84% speedup on different memory request distributions for transaction sizes of 4, 8 and 16. The proposed HTM can be configured to obtain a shorter processing time for different types of applications compared to fixed version management