This paper studies the effect of atomic layer deposition (ALD) temperature on the performance of top-down ZnO nanowire transistors. Electrical characteristics are presented for 10-μm ZnO nanowire field-effect transistors (FETs) and for deposition temperatures in the range 120°C to 210°C. Well-behaved transistor output characteristics are obtained for all deposition temperatures. It is shown that the maximum field-effect mobility occurs for an ALD temperature of 190°C. This maximum field-effect mobility corresponds with a maximum Hall effect bulk mobility and with a ZnO film that is stoichiometric. The optimized transistors have a field-effect mobility of 10 cm(2)/V.s, which is approximately ten times higher than can typically be achieved in...
This work reports an alternative atomic layer deposition (ALD) method to fabricate ZnO thin-film tra...
AbstractThis paper presents a technique involving a sol-gel deposition method applied to the deposit...
New deposition techniques for amorphous oxide semiconductors compatible with silicon back end of lin...
This research project is focused on the optimization and electrical enhancement of zinc oxide (ZnO) ...
Top-down fabrication is used to produce ZnO nanowires by remote plasma enhanced atomic layer deposit...
Top-down fabrication is used to produce ZnO nanowires by remote plasma atomic layer deposition over ...
Top-down fabrication is used to produce ZnO nanowires by remote plasma atomic layer deposition over ...
ZnO thin film transistors (TFTs) are fabricated on Si substrates using atomic layer deposition techn...
Semiconductor nanowires are an emerging class of materials with great potential for applications in ...
ZnO nanowire transistors have shown a great potential in gas and chemical sensing, high power IC, sh...
Cataloged from PDF version of article.ZnO thin film transistors (TFTs) are fabricated on Si substrat...
Thin films of ZnO were deposited by atomic layer deposition (ALD) at different process temperatures ...
The top-down bottom-contact ZnO nanowire field-effect transistors (FETs) utilizing SiO2 as gate diel...
ZnO NWFETs were fabricated with and without Al2O3 passivation. This was done by developing a new rec...
ZnO thin films were deposited by atomic layer deposition (ALD) at various temperatures and the resul...
This work reports an alternative atomic layer deposition (ALD) method to fabricate ZnO thin-film tra...
AbstractThis paper presents a technique involving a sol-gel deposition method applied to the deposit...
New deposition techniques for amorphous oxide semiconductors compatible with silicon back end of lin...
This research project is focused on the optimization and electrical enhancement of zinc oxide (ZnO) ...
Top-down fabrication is used to produce ZnO nanowires by remote plasma enhanced atomic layer deposit...
Top-down fabrication is used to produce ZnO nanowires by remote plasma atomic layer deposition over ...
Top-down fabrication is used to produce ZnO nanowires by remote plasma atomic layer deposition over ...
ZnO thin film transistors (TFTs) are fabricated on Si substrates using atomic layer deposition techn...
Semiconductor nanowires are an emerging class of materials with great potential for applications in ...
ZnO nanowire transistors have shown a great potential in gas and chemical sensing, high power IC, sh...
Cataloged from PDF version of article.ZnO thin film transistors (TFTs) are fabricated on Si substrat...
Thin films of ZnO were deposited by atomic layer deposition (ALD) at different process temperatures ...
The top-down bottom-contact ZnO nanowire field-effect transistors (FETs) utilizing SiO2 as gate diel...
ZnO NWFETs were fabricated with and without Al2O3 passivation. This was done by developing a new rec...
ZnO thin films were deposited by atomic layer deposition (ALD) at various temperatures and the resul...
This work reports an alternative atomic layer deposition (ALD) method to fabricate ZnO thin-film tra...
AbstractThis paper presents a technique involving a sol-gel deposition method applied to the deposit...
New deposition techniques for amorphous oxide semiconductors compatible with silicon back end of lin...