A hardware/software co-design architecture of canny edge detection

The Canny edge detection algorithm has been widely used in image processing and computer vision applications. This algorithm is complex since it requires successive computationally-heavy stages such as smoothing, computing gradient, thinning and thresholding. These steps contain many functions based on multiplications, divisions and arc tan. Hence, processing high quality images using programmable processors such as digital signal processors is slow, multiple processing elements are required. For custom architecture, to efficiently use the hardware resources and improve the processing throughput, some hardware features like pipelining must be employed. This paper proposes a hardware/software co-design architecture which speeds up Canny processing time by 19 times compared to the software implementation. Targeted for NiosII system on Altera FPGA (Field Programmable Gate Array) platform, the co-design provides a balance between hardware acceleration and software reprogram ability