Add to ORKGThe NASA/MSFC high speed CMOS/SOS standard cell family, designed to be compatible with the PR2D (Place, Route in 2-Dimensions) automatic layout program, is described. Standard cell data sheets show the logic diagram, the schematic, the truth table, and propagation delays for each logic cell
A document discusses placing memory modules on the high-speed serial interconnect, which is used by ...
The research is reported for developing a system of computer programs to aid engineering in the desi...
Major silicon-gate CMOS/SOS processes are described. Sapphire substrate preparation is also discusse...
The important features of the multiport (double entry) automatic placement and routing programs for ...
A family of standardized thick-oxide P-MOS building blocks (standard cells) is described. The inform...
The cell placement techniques developed for use with the standard transistor array were incorporated...
A low cost, quick turnaround technique for generating custom metal oxide semiconductor arrays using ...
The CMOS/SOS design rules prepared by the RCA Solid State Technology Center (SSTC) are described. Th...
Two silicon CMOS application specific integrated circuits (ASICs), a data generation chip, and a dat...
The entire complement of standard cells and components, except for the set-reset flip-flop, was comp...
Test data printout tables for cycling performance of Ag Cd, Ag Zn, Ni Cd, Pb Ca, and lead-acid cell
The STAR system developed by NASA enables any user with a logic diagram to design a semicustom digit...
Multiprogramming subsystem implementation by time sharing computer in tracking statio
The design of a MOS 256-bit Random Access Memory (RAM) is discussed. Technological achievements comp...
The application of cellular arrays to NASA missions was studied. Cellular arrays are iterative logic...
A document discusses placing memory modules on the high-speed serial interconnect, which is used by ...
The research is reported for developing a system of computer programs to aid engineering in the desi...
Major silicon-gate CMOS/SOS processes are described. Sapphire substrate preparation is also discusse...
The important features of the multiport (double entry) automatic placement and routing programs for ...
A family of standardized thick-oxide P-MOS building blocks (standard cells) is described. The inform...
The cell placement techniques developed for use with the standard transistor array were incorporated...
A low cost, quick turnaround technique for generating custom metal oxide semiconductor arrays using ...
The CMOS/SOS design rules prepared by the RCA Solid State Technology Center (SSTC) are described. Th...
Two silicon CMOS application specific integrated circuits (ASICs), a data generation chip, and a dat...
The entire complement of standard cells and components, except for the set-reset flip-flop, was comp...
Test data printout tables for cycling performance of Ag Cd, Ag Zn, Ni Cd, Pb Ca, and lead-acid cell
The STAR system developed by NASA enables any user with a logic diagram to design a semicustom digit...
Multiprogramming subsystem implementation by time sharing computer in tracking statio
The design of a MOS 256-bit Random Access Memory (RAM) is discussed. Technological achievements comp...
The application of cellular arrays to NASA missions was studied. Cellular arrays are iterative logic...
A document discusses placing memory modules on the high-speed serial interconnect, which is used by ...
The research is reported for developing a system of computer programs to aid engineering in the desi...
Major silicon-gate CMOS/SOS processes are described. Sapphire substrate preparation is also discusse...