Add to ORKGThe STAR system developed by NASA enables any user with a logic diagram to design a semicustom digital MOS integrated circuit. The system is comprised of a library of standard logic cells and computer programs to place, route, and display designs implemented with cells from the library. Library cells of the CMOS metal gate and CMOS silicon gate technologies were simulated using SPICE, and the results are shown and compared
The work on the Process Analysis Structure was continued with the layout being completed, the 100X a...
The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a uni...
A family of standardized thick-oxide P-MOS building blocks (standard cells) is described. The inform...
The cell placement techniques developed for use with the standard transistor array were incorporated...
An artwork interactive design system is described which provides the microelectronic circuit designe...
The research is reported for developing a system of computer programs to aid engineering in the desi...
Portions of the Computer Aided Design and Test system, a collection of Large Scale Integrated (LSI) ...
A low cost, quick turnaround technique for generating custom metal oxide semiconductor arrays using ...
Digital subsystem design and development employing n-channel and p-channel in MOS FET units in compl...
Internal visual workmanship standards for monolithic microelectronic devices - training manua
Circuit design and mask development sequence are improved by using general purpose computer with int...
Metal oxide semiconductor and GaAs devices are discussed. Digital and analog circuits are described....
The entire complement of standard cells and components, except for the set-reset flip-flop, was comp...
Design and performance of logic circuit chip for computerized design of MOS integrated circuit array
The CMOS/SOS design rules prepared by the RCA Solid State Technology Center (SSTC) are described. Th...
The work on the Process Analysis Structure was continued with the layout being completed, the 100X a...
The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a uni...
A family of standardized thick-oxide P-MOS building blocks (standard cells) is described. The inform...
The cell placement techniques developed for use with the standard transistor array were incorporated...
An artwork interactive design system is described which provides the microelectronic circuit designe...
The research is reported for developing a system of computer programs to aid engineering in the desi...
Portions of the Computer Aided Design and Test system, a collection of Large Scale Integrated (LSI) ...
A low cost, quick turnaround technique for generating custom metal oxide semiconductor arrays using ...
Digital subsystem design and development employing n-channel and p-channel in MOS FET units in compl...
Internal visual workmanship standards for monolithic microelectronic devices - training manua
Circuit design and mask development sequence are improved by using general purpose computer with int...
Metal oxide semiconductor and GaAs devices are discussed. Digital and analog circuits are described....
The entire complement of standard cells and components, except for the set-reset flip-flop, was comp...
Design and performance of logic circuit chip for computerized design of MOS integrated circuit array
The CMOS/SOS design rules prepared by the RCA Solid State Technology Center (SSTC) are described. Th...
The work on the Process Analysis Structure was continued with the layout being completed, the 100X a...
The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a uni...
A family of standardized thick-oxide P-MOS building blocks (standard cells) is described. The inform...