A new basic VLSI circuit element is presented that can be used to realize pulse mode asynchronous sequential circuits. A synthesis procedure is developed along with an unconventional state assignment procedure. Level input asynchronous sequential circuits can be realized by converting a regular flow table into a differential mode flow table, thereby allowing the new synthesis technique to be general. The new circuits tolerate 1-1 crossovers. This circuit also provides a means for state sequence detection and real time fault detection
One step in the synthesis of asynchronous sequential circuits is the construction of a flow table. T...
An iterative logic array (ILA) architecture for synchronous sequential circuits is presented. This t...
This paper presents a high-level notation for designing a VLSI chip as a number of asynchronous stat...
This paper introduces an improved method for designing the class of CMOS VLSI asynchronous sequentia...
One step in the synthesis procedure for realizing an asynchronous sequential circuit that is operati...
This paper describes the known methods of generating next-state equations for asynchronous sequentia...
As the asynchronous sequential circuit has become more and more important to digital systems in rece...
The iterative logic array (ILA) is introduced as a new architecture for asynchronous sequential circ...
A systematic, asynchronous design method based on a flow diagram is shown. The realizat...
Tracey's Theorem has long been recognized as essential in generating state assignments for asynchron...
The idea of introducing redundancy to improve the reliability of digital systems originates from pap...
Journal ArticleRecent practical advances in asynchronous circuit and system design have resulted in ...
An important step in the synthesis procedure for realizing a normal fundamental mode asynchronous se...
Pulse computation is a hybrid of conventional analog and digital techniques which encodes and proces...
A computer aided design (CAD) tool for the design of very large scale integration (VLSI) synchronous...
One step in the synthesis of asynchronous sequential circuits is the construction of a flow table. T...
An iterative logic array (ILA) architecture for synchronous sequential circuits is presented. This t...
This paper presents a high-level notation for designing a VLSI chip as a number of asynchronous stat...
This paper introduces an improved method for designing the class of CMOS VLSI asynchronous sequentia...
One step in the synthesis procedure for realizing an asynchronous sequential circuit that is operati...
This paper describes the known methods of generating next-state equations for asynchronous sequentia...
As the asynchronous sequential circuit has become more and more important to digital systems in rece...
The iterative logic array (ILA) is introduced as a new architecture for asynchronous sequential circ...
A systematic, asynchronous design method based on a flow diagram is shown. The realizat...
Tracey's Theorem has long been recognized as essential in generating state assignments for asynchron...
The idea of introducing redundancy to improve the reliability of digital systems originates from pap...
Journal ArticleRecent practical advances in asynchronous circuit and system design have resulted in ...
An important step in the synthesis procedure for realizing a normal fundamental mode asynchronous se...
Pulse computation is a hybrid of conventional analog and digital techniques which encodes and proces...
A computer aided design (CAD) tool for the design of very large scale integration (VLSI) synchronous...
One step in the synthesis of asynchronous sequential circuits is the construction of a flow table. T...
An iterative logic array (ILA) architecture for synchronous sequential circuits is presented. This t...
This paper presents a high-level notation for designing a VLSI chip as a number of asynchronous stat...