Hardware trade-offs for massive MIMO uplink detection based on Newton iteration method

Massive or large-scale multiple-input multiple-output (MIMO) is an emerging technology for wireless communications and a strong candidate for 5G. Massive MIMO schemes demand heavy computations for precoding, channel estimation and data detection due to the volume of involved data and the requirement for operations such as matrix inversion. Several methods have been proposed for matrix inversion, which take into account complexity conceived at operation level. In this paper, we evaluate Newton's iterative method for matrix inversion for massive MIMO data detection at hardware implementation level and we investigate hardware design aspects targeting FPGA implementation. Also, we appraise different numerical representation of data, considering FPGA resources, throughput rate and BER as metrics and we present a practical implementation with near-optimal BER performance