Photonic Hardware Accelerators for Reservoir Computing

Machine Learning (ML) approaches like Deep Neural Networks (DNNs) have emerged as a powerful tool for big data classification and prediction problems. While feed-forward neural networks are good for non-temporal tasks, a lot of real-world problems like time series prediction (e.g. weather forecasting) and classification problems are temporal in nature. For such problems, Recurrent Neural Networks (RNNs) have been developed. However, the presence of recurrent connections coupled with iterative nature of training algorithms make RNN training extremely hard. Recently, it has been discovered that temporal problems can be solved by network of random recurrent connections coupled with a single trainable readout layer. This is called Reservoir Computing (RC). RC has emerged as a promising area but its implementation is challenging. In Software, RC provides limited performance, whereas hardware implementations have proved to be challenging due to many non-linear nodes present. To solve this problem, we propose to look towards the field of photonic computing to come up with high performance, power efficient photonic hardware accelerators for RC. We integrate ideas from ML, analog photonic computing, photonic device physics and hardware design to build architectures for photonic RC. We design a multi-layer photonic RC architecture to improve the performance of RC. We then integrate Time Division Multiplexing to exploit the inherent parallelism in reservoir layer and design a photonic architecture that is capable of running multiple tasks in parallel. To make photonic RC accelerators scalable, we design a first of its kind architecture that is completely on-chip. Lastly, we study the limitations of the architectures design thus far and design a new kind of reconfigurable architecture that optimizes performance vs power consumption for any given task