Fractional-N PLL with 90 degree phase shift lock and active switched-capacitor loop filter

Phase locked loops (PLL) are used in a variety of RF integrated applications because of their ability to generate precise clock signals. These applications include clock recovery systems, frequency synthesizers and frequency multipliers. In order to achieve small size and low cost targets, the PLLs must be fully integrated on-chip with all the necessary components. Unfortunately, the filtering requirement for the low pass filter (LPF) demands a large silicon area, or the use of external capacitors. Moreover, high-density recording and high data rates for image transfer systems in wireless communication require more fully integrated LSI. The main goal of this study is to find area efficiency with fully on-chip design, and to provide a solution to improve the phase noise level without occupying a large area or using off-chip components. Moreover, to reduce the phase noise level, it is necessary to desensitize the VCO control when the loop is in the "lock zone". The introduced phase noise enhancement (PNE) will smartly reduce the phase noise without degrading the settling time by reducing the loop gain in the lock conditions