A multi polynomial CRC circuit for LTE-Advanced communication standard

Long Term Evolution Advanced (LTE-A) uses four different kinds of Cyclic Redundancy Check (CRC) to verify the integrity of the transmitted data, which implies using four circuits for each CRC in the transceiver system. In this paper, a novel algorithm is introduced to combine three of these CRC circuits into one in order to minimize the total area of the transceiver. This method will insure a considerable reduction in the dynamic power of the system. The new circuit is designed in a parallel fashion and is tested on an Altera FPGA platform to verify its power consumption and number of used gates hence, the total reduction in size. The result shows a good reduction in the number of used logic gates