Correlation between Gate Length, Geometry and Electrostatic Driven Performance in Ultra-Scaled Silicon Nanowire Transistors

—This work investigates the impact of quantum mechanical effects on the device performance of n-type silicon nanowire transistors (NWT) for possible future applications. For the purpose of this paper we have simulated Si NWTs with six various cross-section shapes. However all devices in the crosssectional area is kept constant in order to provide fair comparison between them. Additionally we expanded the computational experiment by including different gate length and gate materials for each of these six Si NWTs. As a result we were able to obtain correlation between the mobile charge distributions in the channel and gate capacitance, drain induced barrier lowering (DIBL) and the sub-threshold slope (SS). The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic speed of the NWTs is also investigated. More importantly all calculations are based on quantum mechanical description of the mobile charge distribution in the channel. This description is based on Schrödinger equation, which is indeed mandatory for nanowires with such nano-scale dimensions