Variability is a critical concern for the stability and yield of SRAM with minimized size. We present a study of a 14 nm node SOI FinFET SRAM cell under the influence of statistical variability and random charge trapping due to positive/negative bias temperature instability (P/NBTI). Low channel doping is believed to be one of the main advantages of FinFETs in reducing statistical variability, but fin and gate edge roughness and metal gate granularity can cause significant variability and affect SRAM stability. The noise margins are largely skewed, and read and write noise margins are decorrelated due to statistical variability. Under heavy stress conditions cell read noise margin can be degraded by 30mV on average due to charge...
Two new six-FinFET memory circuits with asymmetrically gate underlapped bitline access transistors a...
We investigate the impact of negative-bias temperature instability (NBTI) on the degradation of the ...
BSIM-CMG based HSPICE framework is developed for simulating time-zero and Negative Bias Temperature ...
Variability is a critical concern for the stability and yield of SRAM with minimized size. We prese...
Abstract—This paper analyzes the impacts of intrinsic process variations and negative bias temperatu...
This paper presents an evaluation of 14-nm SOI FinFET CMOS SRAM codesign techniques in the presence ...
This paper presents a comprehensive statistical variability study of 14-nm technology node SOI FinFE...
3-D mixed-mode device-circuit simulation is presented to investigate stochastic mismatch of FinFETs ...
none3noWhile traditional scaling used to be accompanied by an improvement in device performance, thi...
Abstract—As planar MOSFETs is approaching its physical scaling limits, FinFET becomes one of the mos...
The impact of fin line-edge roughness on threshold voltage and drive current of LSTP-32nm Fin-FETs i...
A Monte Carlo SPICE framework is proposed to evaluate the impact of negative bias temperature instab...
A comprehensive statistical variability simulation study of a 10nm gate length FinFET device is pres...
We explore the 6T and 8T SRAM design spaces through read static noise margin (RSNM), word-line write...
Threshold voltage ðVT Þ and drive current ðIONÞ variability of low stand-by power (LSTP)-32 nm FinFE...
Two new six-FinFET memory circuits with asymmetrically gate underlapped bitline access transistors a...
We investigate the impact of negative-bias temperature instability (NBTI) on the degradation of the ...
BSIM-CMG based HSPICE framework is developed for simulating time-zero and Negative Bias Temperature ...
Variability is a critical concern for the stability and yield of SRAM with minimized size. We prese...
Abstract—This paper analyzes the impacts of intrinsic process variations and negative bias temperatu...
This paper presents an evaluation of 14-nm SOI FinFET CMOS SRAM codesign techniques in the presence ...
This paper presents a comprehensive statistical variability study of 14-nm technology node SOI FinFE...
3-D mixed-mode device-circuit simulation is presented to investigate stochastic mismatch of FinFETs ...
none3noWhile traditional scaling used to be accompanied by an improvement in device performance, thi...
Abstract—As planar MOSFETs is approaching its physical scaling limits, FinFET becomes one of the mos...
The impact of fin line-edge roughness on threshold voltage and drive current of LSTP-32nm Fin-FETs i...
A Monte Carlo SPICE framework is proposed to evaluate the impact of negative bias temperature instab...
A comprehensive statistical variability simulation study of a 10nm gate length FinFET device is pres...
We explore the 6T and 8T SRAM design spaces through read static noise margin (RSNM), word-line write...
Threshold voltage ðVT Þ and drive current ðIONÞ variability of low stand-by power (LSTP)-32 nm FinFE...
Two new six-FinFET memory circuits with asymmetrically gate underlapped bitline access transistors a...
We investigate the impact of negative-bias temperature instability (NBTI) on the degradation of the ...
BSIM-CMG based HSPICE framework is developed for simulating time-zero and Negative Bias Temperature ...