Study and Comparison of Hardware Methods for Distributing Memory Bank Accesses in Many-core Architectures

International audienceMulti-core and many-core architectures have evolved towards a set of clusters, each cluster being composed of a set of cores communicating with each other through Network-on-Chip. Each cluster integrates cache memory and a local memory shared by all the cores of the cluster. Local memory bandwidth should be able to support all the accesses requested by the cores to get the maximum performance. One solution to reach this objective is to split the local memory in several banks, accessible in parallel. If some cores get access at the same bank simultaneously, this leads to memory bank conflict. A conflict increases the latency for the other cores, decreasing the overall bandwidth.In this work, we start to present in detail when collisions happen and their consequences on the running application. We focus then on hardware solutions to improve the performances of multi-bank accesses, going from hash-function address coding to additional memory banks. All these solutions have been simulated on the MPPA Kalray processor and we provide a comparison and discussions about obtained results, mainly to highlight that there is no universal solution